Method for testing integrated circuits with memory element access

ABSTRACT

A method for testing an integrated circuit having memory elements which are written and/or read via an access path to the memory elements from a terminal external to the circuit. A boundary scan chain is activated to impose and/or observe logic levels on the integrated circuit inputs/outputs.

The present invention relates to processes and devices for testingintegrated circuits as well as the integrated circuits furnished withmeans permitting the carrying out of effective tests.

Two main processes for testing complex integrated logic circuits areknown.

A first process, called the “full scan path automatic test patternvector generation process” or “full scan ATPG” process is commonly usedto test the fabrication of chips.

This process consists in injecting known signals onto pins of theintegrated circuit and in tapping off the values obtained from theoutput pins, so as to compare them with expected values.

This process uses a tester whose channels are linked to the input/outputpins of the integrated circuit. In order to implement this processcorrectly, one requires a tester having a number of channels equal tothe number of input/output pins of the circuit.

With this process, one can test in particular a combinatorial logicfunction. Knowing the combinatorics, one can automatically generate thelogic vectors which make it possible to verify in a quasi-exhaustivemanner the correct implementation of the combinatorics.

However, when the function of the integrated circuit comprises memoryelements, one cannot in general generate the test vectors. In certainrare cases where these vectors can be generated despite the presence ofmemory points, the number of test vectors is very high, so that a verylong test sequence must be implemented, this being difficult to store inmemory, difficult to manipulate, and requiring a great deal of on-testertime.

To avoid this drawback in the case of integrated circuits having memorypoints, one can set in place in the circuit an access path to the memorypoints which makes it possible to read and write from/to all thesememory points, in such a way that the function of the integrated circuitis reduced, by controlling the memory points, to a combinatorialfunction which can be tested.

Customarily, the memory points are placed in series on the access path,this access path being reserved for the test. This path is called the“full scan path”.

This access path adds a few inputs/outputs to the circuit.

This first process comprises a major drawback.

It necessitates a physical access, consisting of a channel of thetester, for each input/output of the integrated circuit. However,nowadays, the number of inputs/outputs of integrated logic circuitscommonly exceeds several hundred, and will soon reach a thousand, andpresent-day testers can in practice only be made with a few hundredchannels. Present-day testers are therefore becoming unsuitable for theintegrated circuits to be tested.

More generally, the higher the number of channels of the testers, themore expensive the latter are.

This drawback is especially acute in the case of large-size circuits,which are most liable to exhibit operating faults. For such circuits,the test is carried out directly on a silicon slice, before lengthy andexpensive mounting of the circuit in a package, which could turn out tobe fruitless since the circuit might be defective. Such an on-slice testis carried out with the aid of a plugboard, whose cost and complexity ofconstruction increase more quickly than the number of plugs, especiallyby reason of a plug coplanarity constraint.

For these reasons, this ATPG method is implemented by linking only someof the input/output pins to the tester. Certain inputs/outputs thereforeremain untested, to the detriment of the quality of the fabricationtest, and areas of the circuit remain untested.

Thus, represented in FIG. 3 is a circuit tested with this known process,on which are indicated, by the reference 10, the unconnected leads, andon which the untested areas have been hatched.

A second process for testing integrated circuits is known, which allowsthe checking and observation of logic levels on the inputs/outputs of acircuit, even when the interconnections of the package are notphysically accessible. This process is used in particular in the case ofa surface-mounted ball grid package (BGA package), or else in the caseof a multilayer printed circuit.

This second type of test, called the “JTAG Boundary Scan”, and definedby the “Joint Test Action Group”, IEEE standard 1149.1, relatesessentially to the testing of printed boards and of the soldering ofintegrated circuits onto these boards. This IEEE standard 1149.1 makesprovision for an access path to the inputs/outputs which is able tosubstitute for a direct physical connection to the inputs/outputs.

This second type of test is implemented by adding logic specific to thistest into the integrated circuit and into the printed board whichcarries it, this logic making it possible, under the control of ahandler called the TAP controller (“Test Access Port controller”), tosense the logic level present on an input, and/or to impose the logiclevel on an output of the integrated circuit. In normal mode, this logicis transparent, both to the inputs and to the outputs.

Thus, the integrated circuits of a board are furnished with an accesspath having the form of a loop and linking in series the set ofinputs/outputs of the relevant circuit, and the loops of each of theintegrated circuits are linked in series.

The Boundary Scan chain therefore runs around the component into whichit is integrated, and also runs around the board receiving thecomponents. A general Boundary Scan chain links the Boundary Scan chainsof each component in series, so that each input/output pad of eachcomponent as well as each track of the board is accessible from outsidethe board, via one and the same path from a specific terminal of theboard, the transfer of the data sensed or to be imposed taking place inseries in this path.

Through such arrangements, the Boundary Scan also permits the testing ofthe interconnections between the integrated circuits on a board. In thiscase, the test vector is loaded serially into the Boundary Scan path,then sent to the interconnections to be tested via output buffers of thecomponents. The results are sampled in the Boundary Scan, via the inputsof the components, then output serially to the tester.

In an “internal test” mode, adapted for testing the componentsthemselves, a test vector is loaded in series in the Boundary Scan pathand then applied to the internal logic of the integrated circuit. Theresult is sampled in the Boundary Scan path, then read serially by thetester.

This second test process has drawbacks: it is especially lengthy toimplement, particularly in the internal mode where the components of theboard are tested. Moreover, this test process turns out to be especiallyunsuitable for the testing of integrated circuits before they aremounted, in particular for testing integrated circuits which comprisememory elements.

U.S. Pat. No. 5,850,513 also discloses a system allowing the checking ofoperational data of a circuit, including a maintenance subsystem, aflash memory, a controller, a processing unit, a main memory module, adata path network, means forming a dual bus, programmable logic controlmeans, an auxiliary data transfer nozzle, and a series of input/outputmodules.

Together, these components process blocks of data of microcodes. Theelements such as associated in this document, do not allow testing ofthe integrated circuit without multiple connections. This document doesnot therefore afford a satisfactory solution to the particularly lengthyimplementation of customary testing processes.

The aim of the invention is to resolve these various drawbacks, byproposing a process for testing integrated circuits not requiring theconnection of all the inputs/outputs of this circuit to a tester andmaking it possible to test an extended area, or even the entire circuit,it being possible moreover for this process to be carried out muchfaster than the known test processes.

Stated otherwise, the invention proposes to improve the coverage of anintegrated circuit fabrication test as compared with the known full-scanATPG method, without increasing the number of channels of the tester.

These aims are achieved according to the invention by virtue of aprocess for testing an integrated circuit comprising memory points and aBoundary Scan chain, in which one writes and/or reads to and/or from thememory points by way of an access path to the memory points from anoutside terminal of the circuit, characterized in that the Boundary Scanchain is activated so as to impose and/or observe logic levels on theinputs/outputs of the integrated circuit.

Other characteristics, aims and advantages of the invention will becomeapparent on reading the detailed description which follows, withreference to the appended figures in which:

FIG. 1 diagrammatically represents a purely combinatorial integratedcircuit in accordance with the state of the art;

FIG. 2 represents an integrated circuit comprising combinatorialfunctions and memory elements in accordance with the state of the art;

FIG. 3 represents the same circuit as in FIG. 2, wherein hatched areasindicate areas not tested when employing an ATPG process of the state ofthe art;

FIG. 4 represents an integrated circuit furnished with a Boundary Scanchain whose inputs and outputs have been represented in detail, inaccordance with the state of the art;

FIG. 5 represents an integrated circuit according to the invention, ofwhich an access path to memory elements has been concatenated with aBoundary Scan path;

FIG. 6 represents an integrated circuit according to the invention, inaccordance with that of FIG. 5, and whose means of connection betweenthe access path to the memory elements and the Boundary Scan path havebeen represented.

Represented on the integrated circuit of FIG. 4 are three main parts:two Boundary Scan input/output modules 20 and 30, and between these twomodules, a part 40 forming the core of the integrated circuit.

The two modules 20 and 30 represented here are identical to one another.Each of the two modules 20 and 30 is placed in parallel with a directlink between a connection pin and the core 40 of the chip.

Only the module 20 will be described, the module 30 comprising the sameelements as the module 20.

The module 20 has two ends, each formed by a multiplexer 22, 24. On alink 23, a first 22 of these two multiplexers receives a control signalcalled “signal shift”, which configures the cell as “shift” or as“load”.

In the case of the cell 20 represented on the left in FIG. 4, themultiplexer 22 is able to receive a pin signal on its first input 21,this being for example a signal received from another chip of the board.

On a second input 23 of the multiplexer 22, the latter receives an inputsignal SI, carrying data transferred into the Boundary Scan chain andwhich data is intended to be loaded by the cell 20 if the latter is in“shift” mode.

Between the two multiplexers 21 and 24, the cell has two registers 25and 26, one of which is a shift register 25 which delivers an outputsignal SO intended to be conveyed in the Boundary Scan to otherinput/output cells (not represented) of the chip 40, or else to otherchips.

The shift register 25 also receives a clock signal denoted ck and theother register 26 receives a signal upd for updating the output latchesof the cell 20, that is to say of memories of the cell 20 which are ableto form a chosen logic level of this input or of this output of theintegrated circuit, when this cell 20 is activated.

The shift register 25 also delivers a signal SO which contains, forcertain cells, information captured on this cell and/or representativeof data recorded in the cell 20, and possibly intended to be analyzed soas to interpret the test.

SI is therefore the serial data input, SO the serial data output.

The multiplexer 24 situated at the other end of the cell 20, that is tosay between the cell 20 and the core 40 of the chip, receives a “mode”signal able to control the cell 20 so that the signal transmitted by thecell 20 to the core of the chip 40 is not the signal received on the pin21 but the signal consisting of the content of the latches of the cell20.

The signals SI and SO are conveyed through the integrated circuit, frominput/output cell to input/output cell over the entire Boundary scanloop linking these inputs/outputs in series.

In a known manner, such an integrated circuit comprises a TAPcontroller, not represented, whose role is to generate the controlsignals SHIFT, UPD, CK and MODE for the Boundary Scan chain of theintegrated circuit.

When testing a board, the TAP controller itself receives control signalsflowing through the Boundary scan path of the board. The instructionsrelating to logic levels to be imposed on certain cells of itsintegrated circuit are transmitted to the TAP controller of the circuitby these control signals. Conversely, logic levels captured on certaincells are also transmitted in the Boundary Scan path by the TAPcontroller.

The integrated circuit according to the invention, which is representedin FIG. 5, comprises a set of pins 100 each associated with aninput/output cell 110. The cells 110 are coupled in series by a BoundaryScan peripheral path 120, represented as a double dashed line. Thisperipheral path 120 therefore forms a loop 110 which runs around theperimeter of the circuit from input/output cell 110 to input/output cell110.

This integrated circuit comprises combinatorial functions 130 and memoryelements 140. The memory elements 140 are interlinked in series by apath 150 which makes it possible to access these memories from anoutside pin 108. This path 150 makes it possible to control, during atest, the memories 140 directly from outside the circuit.

Among the pins 110, certain pins referenced 103 are linked to thechannels of a tester (not represented) and other pins referenced 105 arenot connected to the tester. The connected pins 103 are prolonged inFIG. 5 by a thick line, whereas the unconnected pins 105 merely have ashort thin line.

In accordance with the invention, the testing of this integrated circuitis carried out by acting from outside on the memories 140, whileactivating the Boundary Scan path 120.

The path 150 is used either to place the memories 140 in a predeterminedstate, or else to capture their state in the course of the test.Simultaneously, the Boundary Scan path 120 is used to impose thepredetermined logic levels on certain unconnected inputs/outputs 105 orto capture logic levels to be observed.

Thus, the memories 140 are acted on by way of the path 150 and theunconnected cells 105 are acted on by way of the Boundary Scan path 120.

In this mode of implementation of the invention, chosen signals areinjected into the connected pins, 103 directly through the channels ofthe tester.

The Boundary Scan path 120 being connected to the tester, the testerdispatches into this path a signal chosen specifically to activatecertain of the other cells 105 which are not connected and to impose apredetermined logic level on them.

By using both the Boundary Scan path 120 and a direct connection of thepins 103, the tester has access to all the pins 100 of the integratedcircuit. Any desired test vector can therefore be applied to a set ofpins which encompasses connected pins 103 and unconnected pins 105.

Predetermined levels are applied to groups of input/output pins 100 bycombining an action by direct connection on certain pins with anindirect action on the inputs/outputs by way of the Boundary Scan 120.

The invention also envisages that no pin be acted on directly and thatthe logic levels of the inputs/outputs not be imposed or read other thanby way of the Boundary Scan, whilst acting directly on the memoryelements 140 of the circuit through one or more direct accesses to thesememories 140.

In the case of a circuit with fifteen memory elements for example, it ispossible to adopt fifteen paths for direct access to each of thememories, the Boundary Scan forming a sixteenth control path forelements of the circuit. Of course, it is also possible to place fifteenmemory elements in series on one and the same path as in the case ofFIG. 5.

In the exemplary embodiment of FIG. 5, the access path 150 to the memoryelements 140 is concatenated with the Boundary Scan path 120 so thatthese two paths form one and the same chain on which both the memoryelements 140 and also the input/output cells 110 are placed in series.

Thus, one acts on the memory points 140 and on the input/output cells110 with the sole connection 108 outside the circuit, by injecting theserial data into this chain.

Represented in FIG. 6 is a setup adapted to such concatenation of theBoundary Scan chain 120 and of the chain 150 for direct access to thememories 140. This preferred setup exhibits the advantage of leaving theBoundary Scan path 120 available to the TAP controller when notimplementing the test process according to the invention and of makingit possible to activate the Boundary Scan path 120 during a test of theintegrated circuit carried out in accordance with the invention.

To do this, the chain 150 for access to the memories 140 is linked tothe Boundary Scan chain 120 by way of at least one multiplexercontrolled by a mode signal ATPG-mode, injected from the pin 108.

In a conventional manner, the Boundary Scan chain 120 comprises sixlinks. In FIG. 6, the Boundary Scan path 120 has been depicteddiagrammatically by a simple rectangle furnished with six connectionscorresponding to these links.

Likewise, the assembly formed of the access path 150 with its memoryelements 140 has been represented by a simple rectangle referenced 150.

Represented in detail is the junction between the part of the BoundaryScan chain comprising the cells 110 in series, the TAP controller 200and the access path 140 which here is also called the full-scan ATPGpath by reference to the prior art.

This splice is situated downstream of the TAP controller 200 on theBoundary Scan chain and downstream of the memory points 140 on theaccess path 150.

In this setup, the pin 108 forms the outside end of a set of four linksflowing parallel to one another on the path 150 up to this junction.

These four links are:

-   -   an ATPG-si link able to transmit an information carrier signal        to the memory elements 140 and to the cells 110, controlling        states of certain memories 140 or logic levels of certain        inputs/outputs 110 which are able to recognize the signals which        are specifically intended for them. This ATPG-si channel carries        between the pin 108 and its junction with the Boundary Scan        chain the memory elements 140 arranged in series;    -   an ATPG-se link able to transmit to the Boundary Scan a “shift”        or “load” configuring signal SE for the chosen cells of the        Boundary Scan;    -   a CLOCK link able to transport a clock signal CK to the various        elements of the Boundary Scan, and;    -   an ATPG-mode link able to convey a control signal MODE        indicating whether the Boundary Scan 120 is to be linked to the        controller 200 or else to the chain for access to the memories        150. In the latter case, the Boundary Scan chain 120 is linked        in series to the ATPG chain 150.

The ATPG-mode link is linked to five multiplexers (or equivalentfunctions), each time constituting a control channel thereof.

A first multiplexer 210 receives on a first input the signal SI conveyedon the ATPG-Si link and receives on a second input an input signal SIoriginating from the TAP controller 200.

On its two inputs a second multiplexer 220 respectively receives theclock signal CK coming from the pin 108 and another clock signal CKcoming from the controller 200.

On its inputs a third multiplexer 230 respectively receives the signalSE originating from the pin 108 and the signal SHIFT coming from thecontroller 200.

On its two inputs a fourth multiplexer 240 respectively receives themode signal originating from the controller 200 and a constantactivation signal denoted “1”.

On its two inputs a fifth multiplexer 250 respectively receives theupdating signal UPD originating from the controller 200 and a constantactivation signal denoted “1”.

When the mode signal which is injected into the pin 108 on the ATPG-modelink is at 0, the SI, MODE, Shift, CK and UPD links of the Boundary Scan120 are linked, as in an ordinary circuit, to the controller 200.

Stated otherwise, when no activated test mode signal is transmitted inthe pin 108, the Boundary Scan 120 is linked to its control device 200contrived for carrying out a standard Boundary Scan test.

On the other hand, when a test activation signal is transmitted on theATPG-mode channel of the pin 108, the SI, CK, SHIFT channels of theBoundary Scan 120 are linked respectively to the signals SI, CK, SEapplied respectively to the ATPG-Si, Clock and ATPG-Se links of the pin108, whilst the MODE and UPD links of the Boundary Scan 120 are linkedto the constant activation values equal to 1.

Thus, when the ATPG-mode link of the pin 108 receives an activationsignal, the Boundary Scan path 120 and the cells 110 which it comprisesare controlled by the signals SI, CK and SE applied to the pin 108 fromoutside.

In this same case, the signal MODE and the signal UPD which are receivedby the Boundary Scan chain 120 are the permanent activation signals sothat the content of the latches of the input/output cells of theBoundary Scan is substituted for the signals normally tapped off fromthe pins of these cells during the test according to the invention.

It will be noted that the access path 150 to the memories 140 ispermanently linked to the clock input of the pin 108, unlike theBoundary Scan 120 which is tied to the clock signal of the controller200 or of the pin 108 according to the content of the mode signalapplied to the pin 108.

The output of the Boundary Scan chain 120 forms a pin 109 and alsocarries a link linking this pin 109 to the controller 200, so that theoutput signal SO from the Boundary Scan 120 is looped back onto thecontroller 200.

During the test according to the invention, a tester connected to theATPG-Se, Clock, ATPG-mode and ATPG-Si inputs of the pin 108 activatesthe concatenated chain comprising the memories 140 in series with thecells 110, and applies a chosen state to the memories 140, imposes achosen signal on chosen inputs/outputs 100 of the integrated circuit byway of the Boundary Scan chain, and captures signals obtained oninputs/outputs 100 of the integrated circuit by way of the Boundary Scanchain 120, as well as on the pin 109.

Hence, during the testing of the integrated circuit one uses logicpresent in the circuit, which logic was used hitherto to accessinputs/outputs of the circuit which were inaccessible in particular whenthis circuit was mounted on a board. The coverage of the testing of acomplex integrated logic circuit having numerous inputs/outputs istherefore increased.

A few extra logic gates are added to the circuit so as to couple theBoundary Scan chain 120 to the full-scan ATPG chain, place it innon-transparent mode and couple its clock to the ATPG test clock whenthe test according to the invention is implemented.

The tester is advantageously furnished with a few channels wireddirectly to input/output pins 100 of the circuit.

The tester then comprises a module for injecting test signals directlyinto inputs/outputs linked to these channels and for receiving signalsleaving these inputs/outputs 100, and for comparing them with expectedsignals. The tester then comprises a device for controlling the BoundaryScan chain 120 of the integrated circuit which is coordinated with thedirect injection/reception module so as to generate test vectors on setscomprising both inputs/outputs 103 connected directly to the tester andalso inputs/outputs 105 connected to the tester via the Boundary Scanchain 120.

In the case of such an association of direct injections and injectionsby way of the Boundary Scan chain, the test makes it possible to testall the parts of the circuit and turns out to be especially fast,effective, owing in particular to the fact that one uses a tester whichhas an acceptable number of channels and allows fast and fuller testingof the circuit.

The injecting of the test vectors by the association of direct injectioninto the pins and of injection by way of the Boundary Scan chain mayeven be adopted without resorting to intervention on the memory points.

The concatenating of the ATPG 150 and Boundary Scan 120 chains makes itpossible more generally to act on the memories 140 and on theinput/output cells 110 through one and the same input 108, with one andthe same signal generator.

By virtue of the invention, the number of checking and observationpoints is increased, and hence the coverage of the test in the vicinityof the inputs/outputs which are left unconnected is improved.

The invention improves the testability in the vicinity of thebidirectional inputs/outputs, even those connected to a channel of thetester, since it provides test access to an intermediate point whichaccording to IEEE standard 1149.1 must form part of the boundary scanchain, namely the direction signal.

1. Process for testing an integrated circuit comprising memory pointsand a Boundary Scan chain, in which one writes and/or reads to and/orfrom the memory points by way of an access path to the memory pointsfrom an outside terminal of the circuit, comprising: activating theBoundary Scan chain so as to impose and/or observe logic levels on theinputs/outputs of the integrated circuit.
 2. Process according to claim1, characterized in that the access path to the memory points and theBoundary Scan chain are activated simultaneously.
 3. Process accordingto claim 1 or 2, characterized in that the access path to the memorypoints and the Boundary Scan chain are activated by way of a linecomprising in series the access path to the memory points and theBoundary Scan chain.
 4. Process according to claim 1 or claim 2,characterized in that the Boundary Scan chain is activated by way of anactivation path linked to the Boundary Scan chain downstream of a TAPcontroller.
 5. Process according to claim 4, characterized in that theactivation path is linked to the Boundary Scan chain at least by a logicgate able to link, as a function of a control signal (ATPG-mode), theBoundary Scan chain or else to the activation path of the Boundary Scan,or else to the TAP controller.
 6. Process according to claim 4,characterized in that the activation path includes at least one channel(ATPG-Si) on which is placed at least one memory point, this channelbeing able to be linked in series with the Boundary Scan chain when thelatter is activated.
 7. Process according to claim 1 or claim 2,characterized in that the input channel (Si), clock channel (ck) andconfiguration channel (Sh) of the Boundary Scan chain are linked tologic gates which are able to link, according to a control signal(ATPG-mode), these channels (Si, ck, Sh) or else to the input channel(Si), clock channel (ck) and configuration channel (Sh) of the TAPcontroller or else to the input channel (Si), clock channel (ck) andconfiguration channel (Sh) of the activation path.
 8. Process accordingto claim 1 or claim 2, characterized in that all the memory points arelinked in series.
 9. Process according to claim 1 or claim 2,characterized in that at least some of the inputs/outputs of theintegrated circuit are connected directly to a tester able to injectchosen signals directly into certain of these inputs/outputs, and/or toreceive output signals directly from certain of these inputs/outputs andto compare these output signals with expected signals.
 10. Processaccording to claim 1, claim 2 or claim 9, characterized in that theinjection and/or direct measurement tester is coordinated with a devicefor controlling the Boundary Scan chin so as to generate test vectors onsets comprising both inputs/outputs connected directly to the tester andalso inputs/outputs connected to the tester via the Boundary Scan chain.11. Process according to claim 1 or claim 2, characterized in that thecircuit comprises accesses to its set of memory points and in that thetest is carried out by controlling the set of memory points so that thefunction of the integrated circuit is reduced to a combinatorialfunction.
 12. Integrated circuit comprising a Boundary Scan chain and anaccess path to at least one memory point, characterized in that theaccess path and the Boundary Scan chain are linked in series and in thatthe circuit comprises means for intervening simultaneously on the memorypoint or points of the access path and on the cells of the Boundary Scanchain.
 13. Integrated circuit according to claim 12, characterized inthat the means for intervening simultaneously on the memory point orpoints of the access path and on the cells of the Boundary Scan chaincomprise at least one logic gate able to link the Boundary Scan chain orelse to the access path, or else to a TAP controller.
 14. Integratedcircuit according to claim 12 or claim 13, characterized in that theinput channel (SI), clock channel)(CK) and configuration channel (SHIFT)of the Boundary Scan chain are linked to logic gates which are able tolink, according to a control signal (MODE), these channels or else tothe input channel (SI), clock channel (CK) and configuration channel(SHIFT) of the TAP controller, or else to the input channel (ATPG_si),clock channel (ATPG_ck) and configuration channel (ATPQ_se) of theaccess path.
 15. Integrated circuit according to claim 12 or claim 13,characterized in that all the memory points of the integrated circuitare linked in series.
 16. Integrated circuit tester, comprising: a firstmodule means for imposing and/or reading states of memory points of anintegrated circuit, a second module means for imposing states and/orreading states of input/output cells by way of the Boundary Scan chainof the circuit simultaneously with the action of the first module. 17.Integrated circuit tester according to claim 16, comprising means forsimultaneously injecting into an integrated circuit, control signals(SI) for the memory points and control signals (SI) for theinputs/outputs of the Boundary Scan.
 18. Tester according to claim 16,comprising means for injecting the control signals for the memory pointsand the control signals for the inputs/outputs of the Boundary Scan ontoone and the same channel.
 19. Tester according to any one of claim 16 to18, comprising: a series of channels coupled directly to inputs/outputsof an integrated circuit, and a module means for injecting chosensignals directly into certain of the inputs/outputs, and/or to receiveoutput signals from the inputs/outputs so as to compare the outputsignals with expected signals.
 20. Tester according to claim 19,comprising: a control device for the Boundary Scan chain of anintegrated circuit coordinated with the direct injection/receptionmodule so as to generate test vectors on sets comprising bothinputs/outputs connected directly to the tester and also inputs/outputsconnected to the tester via the Boundary Scan chain.
 21. Testeraccording to one of claims 16 to 18, comprising means for controllingthe set of memory points in such a way that the function of theintegrated circuit is reduced to a combinatorial function during thetest.